1. Field of the Invention
The present invention relates to methods of interconnecting microelectronic elements or microelectromechanical (MEM) elements, e.g., semiconductor chips, integrated circuits and the like and assemblies including semiconductor chips.
2. Description of the Related Art
Microelectronic elements, e.g., semiconductor wafers or semiconductor chips, inter alia, require packaging before they can be incorporated into larger electronic systems. In most cases, semiconductor chips cannot be connected directly to circuit panels, e.g., printed wiring boards, due to electrical reasons, mechanical reasons, or both. Chips require packaging for electrical reasons when the contacts on the chip are too densely packed and too numerous to connect directly to a circuit panel. Packaging may also be required to minimize inductance and capacitance along signal paths to and from a chip. Chips also require packaging for mechanical reasons, due to differences in the materials from which a chip and a printed wiring board typically are made. Because of the differences in materials, when the chip heats up during operation, a chip carrier or substrate to which the chip is connected typically expands at a faster rate than the chip. The chip carrier expands faster because it has a coefficient of thermal expansion (“CTE”) which is higher than that of the chip.
This problem of one element expanding to a different degree than the chip, called “thermal expansion mismatch”, needs to be managed so that the semiconductor chip performs reliably over its entire lifetime. This is especially important for some chips such as processor chips which experience temperature rises during operation of 100° C. or more. In a flip-chip package, especially, solder bumps are used to mount a semiconductor chip to a chip carrier or substrate. In order to lessen thermal expansion mismatch, the chip carrier or substrate can be made from a material having a coefficient of thermal expansion at or close to that of the chip. Such chip carriers or substrates, typically made of glass or ceramic materials, can be expensive to make and harder to work with. Other chip carriers which include polymeric dielectric layers, such as polyimide, for example, are less expensive and may be easier to use, but have a CTE higher than that of semiconductor chips. For example, while silicon has a CTE of 3.5 parts per million per degree C. (ppm/° C.), polyimide typically has a CTE of about 12 to 15 ppm/° C. In such case, the package must be designed to cope with the stresses due to thermal expansion mismatch between the chip and chip carrier which are unavoidable due to the difference between the semiconductor material of the chip and that of the polymeric dielectric layer. In addition, the package must be designed to accommodate thermal expansion of the soldered joints themselves.
Sometimes, an underfill is provided as a layer helping to stiffen the interface between the front face of the chip and the chip carrier or substrate. The underfill limits the movement of the chip relative to the chip carrier and typically fills all the space between the front face of the chip and the chip carrier. In addition, the underfill can be disposed to surround each solder bump individually. The underfill, as well as the material of which the chip carrier is constructed, help manage the stresses in the package due to thermal expansion mismatch.
Traditionally, lead and tin are alloyed together to form a solder. Traditionally, some solders have included a high percentage content of lead, as was used in traditional C4 (“controlled collapse chip connect”) packaging and interconnect technology pioneered by International Business Machines Corporation. A high lead content solder can have a melting temperature of about 375° C., which is significantly higher than that of tin at 232° C. Because of this, solder joints are formed at relatively high melting temperatures, allowing subsequent processes to be performed at higher temperatures as well. At operating temperatures of the chip, lead can have a comparative advantage over tin in that lead is softer than tin and yields to stresses more than tin. Flip-chip packages which include high lead content solder joints can generally withstand internal stresses within the package due to thermal expansion mismatch.
However, recent industry developments are requiring changes in the ways that microelectronic elements are packaged and externally interconnected. For various reasons, lead-free solders are required in applications where until now lead-containing solders had been used. Lead-free solders usually have much greater amounts of tin. Typical lead-free solders such as SnAg, SnCu, SnAgCu, do not yield to stress as much as lead, such that solder bumps formed of lead-free solder can delaminate from their attachment points more readily than lead. Moreover, because they yield less to stress, lead-free solder bumps tend to transfer stress to the chip or the chip carrier more readily than lead-based solder bumps. This can cause the electrical connection formed by the solder bump to break off completely, causing device failures.
Consequently, a current need exists to provide chip packages which are suitable for use in high thermal stress applications, among others, without requiring lead-containing solders to be used. It would further be desirable to provide packages which can withstand high thermal stress and not fail or cause electrical breakages that can cause device failures.